Non-volatile memory devices are widely used in portable systems, such as, for example, laptop computers, personal digital assistants (PDAs), mobile telephones, and various other portable devices and systems. Most of these non-volatile memory devices require a high voltage supply that is internally generated to optimize power consumption of a portable device and that provides a system designer with more. Non-volatile memories store binary information whether or not power is supplied to the memory, which is very useful in portable systems.
Non-volatile memories are realized using floating gate devices, which store information by changing their physical state to two or more physical states. Different physical states are obtained by changing the threshold voltage of the floating gate device by means of injection and extraction of electrons into and out of a floating gate. Injection of electrons into the floating gate results in a higher threshold voltage, corresponding, for example, to a programmed state. Successive extraction of electrons from the floating gate brings down the threshold voltage, corresponding for instance to an erase state. Three or more states can provide operation as multi-level memories.
Injection and extraction of electrons into and out of a floating gate require very high electric fields across the gate oxide and at the terminals of a floating gate device. These high electric fields are obtained by applying voltages higher than the normal power supply voltages. The physical states corresponding to the binary information result in two or more current levels, provided that the non-volatile memory cell is properly biased to read the binary information stored therein by the various charge levels in the floating gate.
For these reasons, non-volatile memories are provided with charge pumps to generate the high voltages needed to accomplished their read or write functions. These high voltages are routed to the memory cells to provide the required electric fields across their gate oxide layers. As a result of using high voltages, the column and row access paths to the memory cell must be realized using devices capable of sustaining high voltages.
FIG. 1 illustrates the organization of a column decoder. A memory device 100 has a memory array 102 with 2n columns. A column decoder 104 routes all of the columns to 2m sense amplifiers 106, where we assume m<n. The memory array 102 is usually formed to have thousands of columns. The number of sense amplifiers may vary from one logical word (16 sense amplifiers) to few words (64 or 128 sense-amplifiers) that are read at the same time.
FIG. 2A illustrates a column decoder 110 having one level of hierarchy so that the number of needed selectors is equal to n (where n is the number of columns) and the number of independent control signals is 2k, where k is defined as k=n−m. FIG. 2B illustrates the column decoder 110 as including 2m groups of selectors transistors, each of the 2m groups having 2k selection transistors with 2k control signals G<1>-G<2k> at respective gates thereof. Because n is an order of magnitude greater than m, a large number of control signals 2k are needed.
FIG. 3 illustrates a configuration where the level of hierarchy is increased to reduce the number of control signals required to connect 2n columns to 2m sense amplifiers. In this configuration, a first column decoder 120 has 2n input columns that are connected to 21 selectors, each having 2j control signals. A second column decoder 122 has 21 input columns that are connected to the 2m sense amplifiers using 2y control signals. It can be shown that: j=n−l, y=l−m, (2j×2y)=2k, and (2j+2y)<<2k. This approach tends to minimize the number of control signals, increases the number of selectors, and attempts to find a trade-off between the number of control signals and the number of selectors.
FIG. 4 is presented to understand one aspect of this approach. FIG. 4 shows a memory 200 organized with multiple sub-arrays 202A, 202B, . . . , 202x, where each sub-array is independent of the other sub-arrays. This organization is very common in non-volatile memory devices, since it improves the performance and the flexibility of the memory. Local columns 204A, 204B, 204x of each sub-array 202A, 202B, . . . , 202x are connected to respective first level column decoders 206A, 204B, . . . , 206x that are routed to global columns 206. A second level of column decoders 208 and, according to the architecture of FIG. 3, a third level of column decoders 210 connect the global column 206 to the sense amplifiers 212. The depth the hierarchy of the column decoder depends on the number of the local columns 204A, 204B, and the number of sense amplifiers 212.
Each of the sub-arrays 202A, 202B, . . . , 202x in FIG. 4 is provided with the high voltage needed for program and erase operations. Recent generation of non-volatile memories perform the erase operation by applying a very high positive voltage to an isolated p-well of the memory array, while the gates of the memory cells are at a negative voltage or at ground potential, depending on the memory architecture or the process characteristics.
FIG. 5 illustrates two single NMOS transistor floating-gate NMOS EEPROM memory cells 250, 252 that are formed in a p-well 254. A source 256 and a drain 258 for the NMOS transistor 250 are formed as doped N-type regions in the p-well 254. A source 260 and a drain 262 for the NMOS transistors 252 are also formed as doped N-type regions in the p-well 254. The drains 258, 262 of these NMOS transistors are connected to a bit line, or column line 264. The source 256, 260 are connected to a source-line 266. The column line 264 provides one column input to a first column decoder 270 that provides selected outputs on the column output line 272. A number of similar EEPROM memory cells are provided in two rows of an EEPROM memory cell array. Each pair of memory cells is connected to a separate bit line or column line. Input signals to he first column decoder 270 select one of a group of bit line.
During an erase operation, the isolated p-well 254 is tied to a high positive voltage. The p-n junctions made by the p-well 254 and the drains 258, 262 of the memory cells are forwarded biased. This results in the local bit-line 264 being tied to the high positive voltage. This means that the first level of column decoders 270 must be realized with transistors capable of sustaining a high voltage like the one needed for the erase operation. This type of high-voltage MOS (HVMOS) transistor has a huge area footprint and poor performance compared with the low-voltage MOS (LVMOS) type of transistors needed for just reading the memory cells. The first level decoder 270 has a number of selector transistors equal to the number of the columns, regardless the number of hierarchical levels of the memory array. Therefore, the first level decoder 270 has a significant effect on the chip area and performance of the memory array, since each sub-array has its own set of column decoders.